Aldec

Description

The Aldec suite provides software used in creation and verification of digital designs targeting field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) technologies. Riviera-PRO addresses verification needs of engineers crafting tomorrow’s cutting-edge FPGA and systems-on-a-chip (SoC) devices. Riviera-PRO enables the ultimate testbench productivity, reusability, and automation by combining the high-performance simulation engine, advanced debugging capabilities at different levels of abstraction, and support for the latest Language and Verification Library Standards. HES-DVM is a fully automated and scriptable Hybrid Verification and Validation environment for SoC and ASIC designs up to 96M ASIC gates capable of bit-level simulation acceleration, SCE-MI 2.1 transaction emulation, hardware prototyping, and virtual modeling. HES-DVM provides hardware design teams with multiple modes of high-speed verification and validation including simulation acceleration, transaction level emulation, and hardware prototyping for chip and system level verification of SoC and ASIC systems.

Version

Riviera-PRO 2013.06.SR1
HES-DVM 2012.06

Authorized Users

Faculty and students in the Computer Science & Engineering Dept.
Faculty and students in the Electrical Engineering Dept.

Platforms

CIRCE cluster
RRA cluster
SC cluster

Modules

Aldec requires the following module file to run:

apps/aldec/2013

See Modules for more information.

Running Aldec on CIRCE

Batch Jobs

Using the shell script example that calls external Riviera-PRO commands to compile and simulate a design from the documentaion listed above, for example, you would set up a submit script like this:

The script below (for testing, name it “aldec-test.sh”) can be copied into your job directory (the folder with your input files) and modified so that you can submit batch processes to the queue.

#!/bin/bash
#
#SBATCH --comment=aldec-test
#SBATCH --ntasks=1
#SBATCH --job-name=aldec-test
#SBATCH --mem-per-cpu=2048
#SBATCH --output=output.%j.aldec-test
#SBATCH --time=01:00:00

#### SLURM 1 processor Aldec test to run for 1 hour.

module load apps/aldec/2013

# create library v_bjack
vlib v_bjack

# compile source files
# working library is specified with -work switch
vlog -work v_bjack src/*.v

# initialize simulation
vsim -c -lib v_bjack V_BJACK_tb –do run.do

Next, you can change to your job’s directory, and run the sbatch command to submit the job:

[user@login0 ~]$ cd my/jobdir
[user@login0 jobdir]$ sbatch ./aldec-test.sh

You can view the status of your job with the “squeue -u <username>” command

Documentation

Home Page, User Guides, and Manuals

Aldec Home Page:
- http://www.aldec.com/en
Riviera-PRO Documentation:
- /apps/aldec/riviera/2013.06/RivieraBatchMode.pdf
- /apps/aldec/riviera/2013.06/RivieraWithGUI.pdf
HES-DVM Documentation:
- /apps/aldec/hes-dvm/2012.06/doc/dvm_product_overview.pdf
- /apps/aldec/hes-dvm/2012.06/doc/hesaccess/hesaccess.pdf
- /apps/aldec/hes-dvm/2012.06/doc/hesprototype/reference_manual.pdf

Benchmarks, Known Tests, Examples, Tutorials, and Other Resources

Riviera-PRO Examples
- /apps/aldec/riviera/2013.06/examples

More Job Information

See the following for more detailed job submission information:

Reporting Bugs

Report bugs with Aldec to the IT Help Desk: rc-help@usf.edu